Energy-efficient and reference-free monotonic capacitor switching scheme with fewest switches for SAR ADC
نویسندگان
چکیده
A novel switching scheme for low energy charge-redistribution digital-to-analog converter (DAC) to be used in successive approximation register (SAR) analogue to-digital converters (ADCs) is presented which requires only 2 references, VREF and ground. With the monotonic capacitor switching procedure and C-2C dummy capacitor, the proposed switching scheme achieves 90.61% less switching energy, 74.7% less area and 41.18% less number of switches compared to conventional architecture, which results in an energy-efficient and switch-fewest switching scheme. Behavioral simulation results prove the effectiveness of the proposed switching scheme.
منابع مشابه
Variable resolution SAR ADC architecture with 99.6% reduction in switching energy over conventional scheme
A novel energy-efficient switching method for variable resolution successive approximation register (SAR) analogue-to-digital converters (ADCs) is presented. The proposed switching scheme achieves switching energy inspired by the early reset merged capacitor switching algorithm (EMCS) and monotonic capacitor switching procedure. Besides, the dummy capacitors are used to further reduce power con...
متن کاملAsymmetric monotonic switching scheme for energy-efficient SAR ADCs
Asymmetric monotonic switching scheme is proposed for a low power successive approximation register (SAR) analogue-to-digital converter (ADC). The proposed switching procedure consumes no energy from reference voltage for the first 3 MSB (most significant bit) conversion using unequal initial DAC setting and asymmetric binary search algorithm. After 3 MSB conversions, DAC switching utilizes a c...
متن کاملEnergy-efficient and area-efficient switching scheme based on multi-reference for SAR ADC
A novel multi-reference capacitor switching scheme for ultralow power successive approximation register (SAR) ADCs is proposed. By using 5 references, the proposed switching scheme only dissipates 10.6 CVREF average energy and requires 256 unit capacitors, which are reduced by 99.2% and 87.5%, compared to the conventional structure. Besides, the common-mode voltage of the comparator input is ap...
متن کاملEnergy efficient asymmetric binary search switching technique for SAR ADC
An asymmetric binary search switching technique for a successive approximation register (SAR) ADC is presented, and trade-off between switching energy and conversion cycles is discussed. Without using any additional switches, the proposed technique consumes 46% less switching energy, for a small input swing (0.5 Vref P-P), as compared to the last reported efficient switching technique in litera...
متن کاملImplemented 5-bit 125-MS/s Successive Approximation Register ADC on FPGA
Implemented 5-bit 125-MS/s successive approximation register (SAR) analog to digital converter (ADC) on FPGA is presented in this paper.The design and modeling of a high performance SAR analog to digital converter are based on monotonic capacitor switching procedure algorithm .Spartan 3 FPGA is chosen for implementing SAR analog to digital converter algorithm. SAR VHDL program writes in Xilinx ...
متن کاملذخیره در منابع من
با ذخیره ی این منبع در منابع من، دسترسی به آن را برای استفاده های بعدی آسان تر کنید
برای دانلود متن کامل این مقاله و بیش از 32 میلیون مقاله دیگر ابتدا ثبت نام کنید
ثبت ناماگر عضو سایت هستید لطفا وارد حساب کاربری خود شوید
ورودعنوان ژورنال:
- IEICE Electronic Express
دوره 12 شماره
صفحات -
تاریخ انتشار 2015